PCI- Express (PCIe,PCI-E)- serial, universal bus first unveiled July 22, 2002 of the year.
Is general, unifying bus for all nodes system board, in which all devices connected to it adjoin. Came to replace an obsolete tire PCI and its variations AGP, due to the increased requirements for bus bandwidth and the impossibility for reasonable means to improve the speed performance of the latter.
The tire acts like switch by simply signaling from one point to another without changing it. This allows, without obvious loss of speed, with minimal changes and errors send and receive a signal.
Data on the bus goes simplex(full duplex), that is, simultaneously in both directions at the same speed, and signal along the lines flows continuously, even if the device is turned off (as D.C., or a bit signal of zeros).
Synchronization constructed by the redundant method. That is, instead of 8 bit information is transmitted 10 bit, two of which are official (20% ) and in a certain sequence serve beacons for synchronization clock generators or error detection. Therefore, the declared speed for one line in 2.5 Gbps, is actually about 2.0 Gbps real.
Food each device on the bus, selected separately and regulated using technology ASPM (Active State Power Management). It allows, when the device is idle (without a signal) underestimate its clock generator and set the bus to reduced power consumption. If no signal is received for a few microseconds, the device considered inactive and switches to the mode expectations(time depends on device type).
Speed characteristics in two directions PCI- Express 1.0 :*
1 x PCI-E~ 500 Mbps
4x PCI-E~ 2 Gbps
8 x PCI-E~ 4 Gbps
16x PCI-E~ 8 Gbps
32x PCI-E~ 16 Gbps
*Data transfer rate in one direction is 2 times lower than these indicators
January 15, 2007 PCI-SIG released an updated specification called PCI Express 2.0
The main improvement was in 2 times increased speed data transmission ( 5.0 GHz, against 2.5GHz in old version). Improvements have also been made point-to-point communication protocol(point-to-point), finalized software component and added system program monitoring for tire speed. At the same time, it preserved compatibility with protocol versions PCI-E 1.x
AT new version standard ( PCI-Express 3.0 ), the main innovation will be modified coding system and synchronization. Instead of 10 bit systems ( 8 bit information, 2 bits service), will apply 130 bit (128 bit information, 2 bits official). This will reduce losses in speed from 20% to ~1.5%. Will also be redesigned synchronization algorithm transmitter and receiver, improved PLL(phase-locked loop).Transmission speed expected to increase 2 times(compared to PCI-E2.0), wherein compatibility will remain with previous versions PCI-Express.
Interface support PCI Express 3.0 in motherboards - a real advantage or a marketing ploy?
During the last months in model range different manufacturers motherboards began to appear, which declared support for the PCI Express 3.0 interface. ASRock, MSI and GIGABYTE were the first to announce such solutions. However, on this moment, there are absolutely no chipsets, graphics and central processors on the market that would support the PCI Express 3.0 interface.
Recall that the PCI Express 3.0 standard was approved last year. It has numerous advantages over its predecessors, so it is not surprising that graphics card and motherboard manufacturers want to implement it in their solutions as soon as possible. However, currently existing chipsets from Intel companies and AMD are limited to supporting the PCI Express 2.0 standard. The only hope to take advantage of the PCI Express 3.0 interface in the near future lies with the new Intel Ivy Bridge processors, which are scheduled to be announced only in March-April next year. These processors have an integrated PCI Express 3.0 bus controller, but only graphics chips will be able to use it, since other components use the chipset controller.
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Note that the matter is not limited to just replacing the processor. Additional update needed BIOS settings and chipset firmware. In addition, on motherboards with several PCI Express x16 slots, there is a problem with "switches" - small microcircuits that are located near each slot and are responsible for the operational reconfiguration of the number of dedicated lines. These "switches" must also be compatible with the PCI Express 3.0 interface. It should be noted that nForce 200 or Lucid bridge chips support only the PCI Express 2.0 standard and they cannot work with the PCI Express 3.0 specification.
The last argument is that at the moment motherboard manufacturers do not have engineering samples new processors Intel line Ivy Bridge or new graphics chips that support the PCI Express 3.0 specification at the hardware level. Therefore, the announced compatibility with this high-speed interface is theoretical and cannot, at the moment, be practically confirmed.
Thus, support for the PCI Express 3.0 specification by modern motherboards is purely a marketing ploy, the benefits from which the user will be able to get only in a few months by replacing the processor and updating software components.
Attention! This article is about the PCI bus and its PCI64 and PCI-X derivatives! Do not confuse it with the newer tire ("PCI Express"), which is completely incompatible with the tires described in this FAQ.
PCI 2.0- the first version of the basic standard, which was widely used, both cards and slots with a signal voltage of only 5V were used. PCI 2.1- differed from 2.0 by the possibility of simultaneous operation of several bus-master devices (the so-called competitive mode), as well as the appearance of universal expansion cards capable of operating in both 5V and 3.3V slots. The ability to work with 3.3V cards and the presence of appropriate power lines in version 2.1 was optional. PCI66 and PCI64 extensions appeared.
PCI 2.2- a version of the basic bus standard that allows connection of expansion cards with a signal voltage of both 5V and 3.3V. The 32-bit versions of these standards were the most common slot type at the time the FAQ was written. 32-bit, 5V type slots are used.
Expansion cards made in accordance with these standards have universal connector and are able to work in almost all later varieties of PCI bus slots, and also, in some cases, in 2.1 slots.
PCI 2.3 - next version common standard to the PCI bus, expansion slots conforming to this standard are not compatible with 5V PCI cards, despite the continued use of 32-bit 5V-keyed slots. Expansion cards have a universal connector, but are not able to work in 5V slots of earlier versions (up to 2.1 inclusive).
We remind you that the supply voltage (not signal!) 5V is stored absolutely on all versions of the PCI bus connectors.
PCI 64- an extension of the basic PCI standard, introduced in version 2.1, doubling the number of data lines, and, consequently, the throughput. The PCI64 slot is an extended version of the regular PCI slot. Formally, the compatibility of 32-bit cards with 64-bit slots (subject to the presence of a common supported signal voltage) is complete, and the compatibility of a 64-bit card with 32-bit slots is limited (in any case, there will be a loss of performance), exact data in each case can be found in the specifications of the device.
The first versions of PCI64 (derived from PCI 2.1) used a 64-bit 5V PCI slot and ran at 33MHz.
PCI 66- an extension of the PCI standard that appeared in version 2.1 with support for a clock frequency of 66 MHz, as well as PCI64, allows you to double the bandwidth. Starting with version 2.2, it uses 3.3V slots (the 32-bit version is almost never found on a PC), cards have a universal or 3.3V form factor. (There were also solutions based on version 2.1, casuistically rare on the PC 5V 66MHz market, such slots and boards were only compatible with each other)
PCI 64/66- A combination of the above two technologies, it can quadruple the data transfer rate compared to the basic PCI standard, and uses 64-bit 3.3V slots, compatible only with universal and 3.3V 32-bit expansion cards. PCI64/66 cards have a universal (with limited compatibility with 32-bit slots) or 3.3V form factor (the latter option is fundamentally not compatible with 32-bit 33MHz slots of popular standards)
Currently, the term PCI64 means exactly PCI64/66, since 33MHz 5V 64-bit slots have not been used for a long time.
PCI-X 1.0- Expansion of PCI64 with the addition of two new operating frequencies, 100 and 133 MHz, as well as a separate transaction mechanism to improve performance when running multiple devices at the same time. Generally backwards compatible with all 3.3V and universal PCI cards.
PCI-X cards are usually implemented in 64-bit 3.3B format and have limited backward compatibility with PCI64/66 slots, and some PCI-X cards are in a universal format and can work (although this has almost no practical value) in regular PCI 2.2/2.3.
In difficult cases, in order to be completely confident in the performance of the combination of motherboard and expansion card you have chosen, in the case you need to look at the compatibility lists of the manufacturers of both devices.
PCI-X 2.0- further expansion of the capabilities of PCI-X 1.0, added speeds of 266 and 533 MHz, as well as parity error correction during data transfer. (ECC). Allows splitting into 4 independent 16-bit buses, which is used exclusively in embedded and industrial systems, the signal voltage is reduced to 1.5V, but the connectors are backward compatible with all cards using a 3.3V signal voltage.
PCI-X 1066/PCI-X 2133- projected future versions of the PCI-X bus, with resulting operating frequencies of 1066 and 2133 MHz, respectively, originally intended for connecting 10 and 40 Gbit Ethernet adapters.
For all variants of the PCI-X bus, there are the following restrictions on the number of devices connected to each bus:
66MHz - 4
100MHz - 2
133MHz - 1 (2, if one or both devices are not on expansion boards, but are already integrated on one board along with the controller)
266.533MHz and above -1.
That is why, in some situations, to ensure the stability of several installed devices need to limit maximum frequency operation of the used PCI-X bus (usually this is done by jumpers)
CompactPCI- a standard for connectors and expansion cards used in industrial and embedded computers. Mechanically not compatible with any of the "common" standards.
MiniPCI- a standard for boards and connectors for integration into laptops (usually used for adapters wireless network) and directly to the surface. It is also mechanically incompatible with anything other than itself.
Types of PCI expansion cards:
Summary table of constructs of cards and slots depending on the version of the standard:
Summary table of compatibility of cards and slots depending on the version and design:
| Cards | ||||||||
| Slots | PCI 2.0/2.1 5B | PCI 2.1 generic | PCI 2.2/2.3 universal | PCI64/5B (33MHz) |
PCI64/universal | PCI64/3.3B | PCI-X/3.3B | PCI-X universal |
| PCI 2.0 | Compatible | Compatible | Incompatible | Limited compatibility with performance loss | Incompatible | |||
| PCI 2.1 | Compatible | Compatible | Limited compatible | Limited compatibility with performance loss | Limited compatibility with performance loss | Incompatible | ||
| PCI 2.2 | Compatible | Limited compatibility with performance loss | Limited compatibility with performance loss | Incompatible | Incompatible | Limited compatibility with performance loss | ||
| PCI 2.3 | Incompatible | Limited compatible | Compatible | Incompatible | Limited compatibility with performance loss | Incompatible | Incompatible | Limited compatibility with performance loss |
| PCIB 64/5B(33MHz) |
Compatible | Compatible | Limited compatible | Compatible | Limited compatibility with performance loss | Incompatible | Incompatible | Limited compatibility with performance loss |
| PCI64/3.3B | Incompatible | Limited compatible | Compatible | Incompatible | Compatible | Compatible | Limited compatibility with performance loss | Limited compatibility with performance loss |
| PCI-X | Incompatible | Limited compatible | Compatible | Incompatible | Compatible | |||
The PCI Express serial bus, developed by Intel and its partners, is designed to replace the parallel PCI bus and its extended and specialized variant AGP. Despite similar names, PCI and PCI Express buses have little in common. The parallel data transfer protocol used by PCI imposes limits on the bandwidth and frequency of the bus; the serial data transfer used in PCI Express provides scalability (the specifications describe implementations of PCI Express 1x, 2x, 4x, 8x, 16x and 32x). At the moment, the tire version with index 3.0 is relevant.
PCI-E3.0
In November 2010, the PCI-SIG organization, which standardizes PCI Express technology, announced the adoption of the PCIe Base 3.0 specification.
The key difference from the previous two versions of PCIe can be considered a changed coding scheme - now instead of 8 bits useful information out of 10 bits transmitted (8b / 10b), 128 bits of useful information can be transmitted over the bus out of 130 bits sent, i.e. The payload ratio is close to 100%. In addition, the data transfer rate has increased to 8 GT/s. Recall that this value for PCIe 1.x was 2.5 GT/s, and for PCIe 2.x it was 5 GT/s.
All of the above changes resulted in a doubling of the bus bandwidth compared to the PCI-E 2.x bus. This means that the total bandwidth of the PCIe 3.0 bus in a 16x configuration will reach 32 Gb / s. The first processors to be equipped with a PCIe 3.0 controller were Intel processors based on the Ivy Bridge microarchitecture.
Despite more than three times the throughput of PCI-E 3.0 compared to PCI-E 1.1, the performance of the same video cards when using different interfaces does not differ much. The table below shows the test results GeForce GTX 980 in various tests. The measurements were carried out with the same graphics settings, in the same configuration. The PCI-E bus version was changed in the BIOS settings.
PCI Express 3.0 continues to be backward compatible with previous versions PCIe.
PCI-E 2.0
In 2007, a new specification for the PCI Express bus - 2.0 was adopted, the main difference of which is the doubled bandwidth of each transmission line in each direction, i.e. in the case of the most popular version of PCI-E 16x used in video cards, the throughput is 8Gb / s in each direction. The first chipset with PCI-E support 2.0 became the Intel X38.
PCI-E 2.0 is fully backward compatible with PCI-E 1.0, i.e. all existing devices PCI-E interface 1.0 slots can work in PCI-E 2.0 slots and vice versa.
PCI-E 1.1
The first version of the PCI Express interface, introduced in 2002. Provided throughput of 500 MB / s per line.
Comparison of the speed of work of different generations of PCI-E
The PCI bus runs at 33 or 66 MHz and provides 133 or 266 MB/s bandwidth, but this bandwidth is shared among all PCI devices. The frequency at which the PCI Express 1.1 bus operates is 2.5 GHz, which gives a bandwidth of 2500 MHz / 10 * 8 = 250 * 8 Mbps = 250 Mbps information) for each PCI Express 1.1 x1 device in one direction. If there are several lines, to calculate the throughput, the value of 250 Mb / s must be multiplied by the number of lines and by 2, because. PCI Express is a bidirectional bus.
| Number of PCI Express 1.1 lanes | Throughput in one direction | Total throughput |
| 1 | 250 MB/s | 500 MB/s |
| 2 | 500 Mb/s | 1 GB/s |
| 4 | 1 GB/s | 2 GB/s |
| 8 | 2 GB/s | 4 GB/s |
| 16 | 4 GB/s | 8 GB/s |
| 32 | 8 GB/s | 16 GB/s |
Note! You should not attempt to install a PCI Express card in a PCI slot, and conversely, PCI cards are not installed in PCI Express slots. However, a PCI Express 1x card, for example, can be installed and most likely will function normally in a PCI Express 8x or 16x slot, but not vice versa: a PCI Express 16x card will not fit into a PCI Express 1x slot.
In this article, we will explain the reasons for the success of the PCI bus and describe the high-performance technology that is coming to replace it - the PCI Express bus. We will also look at the history of development, the hardware and software levels of the PCI Express bus, the features of its implementation and list its advantages.
When in the early 1990s she appeared, then on her own technical specifications significantly outperformed all buses that existed up to that point, such as ISA, EISA, MCA and VL-bus. At that time, the PCI bus (Peripheral Component Interconnect - interaction of peripheral components), operating at a frequency of 33 MHz, was well suited for most peripherals. But today the situation has changed in many ways. First of all, the clock speeds of the processor and memory have increased significantly. For example, the clock frequency of processors has increased from 33 MHz to several GHz, while the operating frequency of PCI has increased to only 66 MHz. The emergence of technologies such as Gigabit Ethernet and IEEE 1394B threatened that the entire bandwidth of the PCI bus could go to serve a single device based on these technologies.
At the same time, the PCI architecture has a number of advantages over its predecessors, so it was not rational to completely revise it. First of all, it does not depend on the type of processor, it supports buffer isolation, bus mastering technology (bus capture) and PnP technology in full. Buffer isolation means that the PCI bus operates independently of the internal processor bus, which allows the processor bus to function independently of the speed and load of the system bus. Thanks to the bus capture technology, peripheral devices have the ability to directly control the process of data transfer on the bus, instead of waiting for help from CPU which would affect system performance. Finally, Plug and Play support allows automatic tuning and configuring the devices that use it and avoid fussing with jumpers and switches, which pretty much ruined the life of the owners of ISA devices.
Despite the undoubted success of PCI, at the present time it faces serious problems. Among them are limited bandwidth, lack of real-time data transmission functions and lack of support for next-generation network technologies.
Comparative characteristics of various PCI standards
It should be noted that the actual throughput may be less than the theoretical one due to the principle of the protocol and the features of the bus topology. In addition, the total bandwidth is distributed among all devices connected to it, therefore, than more devices sits on the bus, the less bandwidth goes to each of them.
Such standard improvements as PCI-X and AGP were designed to eliminate its main drawback - low clock speed. However, increasing the clock frequency in these implementations has resulted in a reduction in the effective length of the bus and the number of connectors.
The new generation of the bus, PCI Express (or PCI-E for short), was first introduced in 2004 and was designed to solve all the problems that its predecessor faced. Today, most new computers are equipped with a PCI Express bus. Although they also have standard PCI slots, the time is not far off when the bus will become history.
PCI Express Architecture
The bus architecture has a layered structure as shown in the figure.
The bus supports the PCI addressing model, which allows all currently existing drivers and applications to work with it. In addition, the PCI Express bus uses the standard PnP mechanism provided by the previous standard.
Consider the purpose of the various levels of organization PCI-E. At the software level of the bus, read / write requests are generated, which are transmitted at the transport level using a special packet protocol. The data layer is responsible for error-correcting coding and ensures data integrity. The basic hardware layer consists of a double simplex channel consisting of a transmit and receive pair, collectively referred to as a line. The total bus speed of 2.5 Gb/s means that the throughput for each PCI Express lane is 250 Mb/s each way. If we take into account the overhead costs of the protocol, then about 200 Mb / s is available for each device. This throughput is 2-4 times higher than what was available for PCI devices. And, unlike PCI, if the bandwidth is distributed among all devices, then it goes to each device in full.
To date, there are several versions of the PCI Express standard, which differ in their bandwidth.
PCI Express x16 bus bandwidth for different PCI-E versions, Gb/s:
- 32/64
- 64/128
- 128/256
PCI-E bus formats
At the moment, various options for PCI Express formats are available, depending on the purpose of the platform - a desktop computer, laptop or server. Servers that require more bandwidth have more PCI-E slots, and those slots have more trunks. In contrast, laptops may only have one line for medium-speed devices.
Video card with PCI Express x16 interface.
PCI Express expansion cards are very similar to PCI cards, but the PCI-E connectors are more grippy to ensure the card won't slip out of the slot due to vibration or during shipping. There are several form factors of PCI Express slots, the size of which depends on the number of lanes used. For example, a bus with 16 lanes is referred to as PCI Express x16. Although the total number of lanes can be as high as 32, in practice, most motherboards nowadays are equipped with a PCI Express x16 bus.
Smaller form factor cards can be plugged into larger form factor slots without compromising performance. For example, a PCI Express x1 card can be plugged into a PCI Express x16 slot. As in the case of the PCI bus, you can use a PCI Express extender to connect devices if necessary.
The appearance of the connectors various types on the motherboard. From top to bottom: PCI-X slot, PCI Express x8 slot, PCI slot, PCI Express x16 slot.
Express Card
The Express Card standard offers a very simple way to add hardware to a system. The target market for Express Card modules are laptops and small PCs. Unlike traditional expansion boards desktop computers, the Express card can connect to the system at any time while the computer is running.
One of the popular varieties of Express Card is the PCI Express Mini Card, designed as a replacement for Mini PCI form factor cards. A card created in this format supports both PCI Express and USB 2.0. PCI Express Mini Card dimensions are 30×56 mm. PCI card Express Mini Card can connect to PCI Express x1.
Benefits of PCI-E
PCI Express technology has gained advantages over PCI in the following five areas:
- Better performance. With just one lane, the throughput of PCI Express is twice that of PCI. In this case, the throughput increases in proportion to the number of lines in the bus, maximum amount which can be up to 32. An additional advantage is that information on the bus can be transmitted simultaneously in both directions.
- Simplification of input-output. PCI Express takes advantage of buses such as AGP and PCI-X with a less complex architecture and relatively simple implementation.
- Layered architecture. PCI Express offers an architecture that can adapt to new technologies without the need for significant software upgrades.
- New generation I/O technologies. PCI Express gives you new opportunities to receive data with the help of simultaneous data transfer technology, which ensures that information is received in a timely manner.
- Ease of use. PCI-E greatly simplifies system upgrades and expansions by the user. Additional formats Express boards, such as ExpressCard, greatly increase the possibility of adding high-speed peripherals to servers and laptops.
Conclusion
PCI Express is a bus technology for connecting peripherals, replacing technologies such as ISA, AGP, and PCI. Its use significantly increases the performance of the computer, as well as the user's ability to expand and update the system.